IBM announced a semiconductor technology breakthrough with the introduction of the world’s first sub-1 nanometer (nm) chip technology, featuring a transistor architecture at the 0.7 nm (7 angstrom) node. The development addresses the physical limits of traditional chip scaling in an industry where semiconductors are critical to computing, appliances, communication devices, transportation systems, and infrastructure.
The new sub-1 nm chip houses nearly 100 billion transistors on a chip the size of a fingernail, doubling the density of IBM’s 2 nm chip introduced in 2021. Enabled by structural and material innovations, including a three-dimensional nanostack architecture, the technology maintains performance and efficiency gains as features approach atomic dimensions. Published technical results indicate the chip is projected to deliver up to 50 percent more performance or 70 percent greater energy efficiency compared to IBM’s 2 nm node chips, targeting workloads in generative AI, cloud infrastructure, and next-generation electronic devices.
Jay Gambetta, Director of IBM Research and IBM Fellow, stated that the nanostack architecture reinvents how chips are built to deliver increased power and energy efficiency, moving technology beyond the nanometer era to the scale of atoms to establish a foundation for future computing.
To manufacture the chip, researchers developed a transistor architecture called “nanostack,” which is the industry’s first three-dimensional, nanosheet-based design. Advancing beyond IBM’s previous nanosheet technology, the nanostack design vertically stacks and staggers transistors using 3D sequential integration to increase transistor density. This design allows for different material combinations within each stacked layer, optimizing individual transistor performance and power efficiency.
The architecture was experimentally validated through ultra-thin dielectric bonding in CMOS integration, dual-channel engineering capability, and functional CMOS inverter operation with expected switching performance.
Additionally, research presented at VLSI 2026 demonstrated that the nanostack architecture provides a 40 percent scaling in SRAM, allowing designers to build more efficient chips capable of supporting high-bandwidth data demands for advanced AI workloads. The 0.7 nm technology extends logic technology below the 1 nm node into angstrom-level scaling. IBM’s semiconductor roadmap projects that this new architecture will extend future scaling for at least a decade.
This breakthrough follows IBM’s historical semiconductor developments, which include early semiconductors in the 1960s and the world’s first 2 nm node chip. IBM and its partners conduct this research at a facility in Albany, New York, which is scheduled to house a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool developed by ASML for ultra-precise circuit printing. IBM has partnered with Lam Research Corp., Tokyo Electron (TEL), and SCREEN Semiconductor Solutions, Ltd. to develop High NA EUV processes and tools, which have already produced working devices.
IBM also recently announced plans to form Anderon, a standalone pure-play quantum foundry. Anderon will utilize IBM’s quantum computing and semiconductor expertise to manufacture quantum wafers in the United States. With the initial adoption of nanostack technology at the sub-1 nm node, IBM projects a path to production within the next five years.
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